Semiconductor memory device with controllable operation...

Details Semiconductor memory device with controllable operation... Semiconductor memory device with controllable operation...

2001-08-17

2002-11-12

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S189090, C365S230040

Reexamination Certificate

active

06480435

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and particularly to a semiconductor memory device structured to achieve control of the operation timing of a sense amplifier.
2. Description of the Background Art
A conventional dynamic random access memory is described with regard to a structure of its main portion. It is noted that a signal name having “Z” at the head represents a signal of active L. Referring to
FIG. 13
, the conventional semiconductor memory device includes a plurality of memory cells
1
, a plurality of word lines WL arranged in the row direction, and a plurality of paired bit lines BL<i> and ZBL<i> (i=0, 1, . . . ) arranged in the column direction.
Each bit line pair is connected to a data bus (not shown) via a sense amplifier unit
2
. Paired bit lines BL <k> and ZBL <k> are connected to a sense amplifier unit
2
included in a sense amplifier block SB
0
located on the left side with respect to the memory region while paired bit lines BL <k+1> and ZBL <k+1> are connected to a sense amplifier unit
2
included in a sense amplifier block SB
1
located on the right side with respect to the memory region (k=0, 2, 4, . . . ).
Referring to
FIG. 14
, sense amplifier unit
2
includes a sense amplifier SA for detecting a potential difference of a corresponding bit line pair, and an equalize·precharge circuit EQ for equalizing and precharging a corresponding bit line pair.
Referring again to
FIG. 13
, sense amplifier SA included in sense amplifier block SB
0
is activated by a sense amplifier activation signal SON <
0
> and sense amplifier SA included in sense amplifier block SB
1
is activated by a sense amplifier activation signal SON <
1
>.
Equalize·precharge circuit EQ electrically connects, in response to an equalize signal EQ, a line VBL supplying a reference voltage VBL to a corresponding bit line pair at a predetermined timing.
For writing of data into a memory cell as well as reading of data from a memory cell, a bit line pair is precharged to reference potential VBL in advance.
In the reading operation, externally applied address signals ext.A
0
to ext.A
12
drive a corresponding word line WL into H level. Data in each memory cell
1
connected to that word line WL is read to cause change in the potential on the bit line. Following this, the sense amplifier activation signal goes to H level. Sense amplifier SA differentially amplifies a potential difference between paired bit lines to define data on the bit line pair as “H” or “L”.
As shown in
FIG. 15
, sense amplifier SA includes PMOS transistors T
0
to T
2
, NMOS transistors T
3
to T
5
, and an inverter I
0
.
Transistor T
0
is connected between a node Vcc receiving a supply voltage and a node Z
0
and has its gate receiving an output of inverter I
0
. Transistor T
5
is connected between a node Z
1
and a node GND receiving a ground voltage and has its gate receiving sense amplifier activation signal SON. Inverter I
0
inverts sense amplifier activation signal SON and outputs the inverted signal.
Transistor T
1
is connected between nodes Z
0
and Z
3
and transistor T
3
is connected between nodes Z
3
and Z
1
. Transistor T
2
is connected between nodes Z
0
and Z
4
and transistor T
4
is connected between nodes Z
4
and Z
1
. Respective gates of transistors T
1
and T
3
are connected at node Z
4
to bit line BL and respective gates of transistors T
2
and T
4
are connected at node Z
3
to bit line ZBL. When sense amplifier activation signal SON goes H, one of the bit lines is driven to the GND level and the other bit line is driven to the Vcc level according to a potential difference of the bit line pair.
Sense amplifier SA and a control circuit have a relation as described below in conjunction with FIG.
16
. Referring to
FIG. 16
, the conventional semiconductor memory device includes an internal circuit
100
receiving an external row address strobe signal ext.ZRAS to output an internal signal ZSONM, a block selection circuit
102
receiving external address signals ext.A
0
to ext.A
12
to output block selection signals BS<
0
> to BS<
15
>, a VBL generating circuit
104
generating reference voltage VBL, a sense amplifier activation signal generating circuit
106
receiving the block selection signals and internal signal ZSONM to output sense amplifier activation signals SON<
0
> SON<
15
>, and memory array blocks B
0
, B
1
, . . . .
A combination of external address signals ext.A
0
to ext.A
12
causes activation of block selection signals BS<j> and BS<j+
1
>for selecting adjacent memory array blocks Bj and Bj+
1
among block selection signals BS<
0
> to BS<
15
>.
Sense amplifier activation signal generating circuit
106
includes logic circuits
5
#
0
,
5
#
1
, . . . and inverters I
1
#
0
, I
1
#
1
, . . . arranged respectively corresponding to sense amplifier activation signals SON<
0
>, SON<
1
>, Logic circuit
5
#i receives at its inputs internal signal ZSONM and block selection signal BS<i>. Inverter I
1
#i inverts an output of logic circuit
5
#
1
to output sense amplifier activation signal SON<i>.
When block selection signal BS<i> is “H” and internal signal ZSONM is “L”, sense amplifier activation signal SON<i> goes “H”. Sense amplifier activation signal SON<I> is supplied to memory array block Bi.
Memory array block Bi includes sense amplifier SA activated by sense amplifier activation signal SON<i>, memory cells holding data to be read by that sense amplifier SA, a plurality of bit line pairs provided corresponding to the memory cells, and equalize·precharge circuit EQ for equalizing and precharging the bit line pairs.
Memory array block Bk includes paired bit lines BL<i> and ZBL<i> as well as sense amplifier block SB
0
including sense amplifier unit
2
connected to the paired bit lines BL<i> and ZBL<i> in FIG.
13
. Memory array block Bk+
1
includes paired bit lines BL<i+
1
> and ZBL<i+
1
> as well as sense amplifier block SB
1
including sense amplifier unit
2
connected to the paired bit lines BL<i+1> and ZBL<i+1> in
FIG. 13
(k=0, 2, 4, . . . , i=0, 2, 4, . . . ).
All memory array blocks Bi are supplied with reference voltage VBL from VBL generating circuit
104
.
An operation of the conventional semiconductor memory device is now described. External row address strobe signal ext.ZRAS goes “L”. Address signals which are input at this time cause a specific word line WL to be driven into “H”. Data of each memory cell connected to the word line WL is output onto bit line ZBL. Internal signal ZSONM goes “L” with a certain delay from the rise timing of word line WL.
It is supposed here that a combination of external input signals ext.A
0
to ext.A
12
causes block selection signals BS<
0
> and BS<
1
>for example to become “H”.
Signal ZSONM is “L” and signals BS<
0
> and BS<
1
> are “H”. Then, sense amplifier activation signals SON<
0
> and SON<
1
> go “H”. Sense amplifier activation signals SON<
0
> and SON<
1
> at “H” activate sense amplifier SA so that data of respective bit lines BL and ZBL are defined as “H” or “L”.
The performance of memory cells in such a conventional semiconductor memory device is evaluated through the procedure described below. First, a specific memory cell (object cell) is written with “L” data, memory cells adjacent to the object cell and connected to the same word line WL as that to which the object cell is connected are written with “L” data, and other memory cells connected to that word line WL are all written with “H” data. (This write pattern is herein referred to as a three-sense amplifier pattern.) Then, data of the object cell is read.
It is assumed here that the object cell is connected to paired bit lines BL<
3
> and ZBL<

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