Semiconductor memory device with ferroelectric device

Details Semiconductor memory device with ferroelectric device Semiconductor memory device with ferroelectric device

2007-12-31

2010-02-23

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S145000

Reexamination Certificate

active

07668031

ABSTRACT:
A semiconductor memory device includes a one-transistor (1-T) field effect transistor (FET) type memory cell connected between a pair of bit lines, and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer. The device includes a plurality of word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a pair of clamp dummy lines arranged in the column direction, a pair of reference dummy lines arranged in the column direction, a cell array including the memory cell and formed in a region where the word line and the bit line are crossed, a dummy cell array including the memory cell and formed where the word line, the pair of claim dummy lines and the pair of reference dummy lines are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.

REFERENCES:
patent: 6026009 (2000-02-01), Choi et al.
patent: 2003/0206430 (2003-11-01), Ho
patent: 10-2005-0127038 (2007-04-01), None
patent: 10-2006-0070964 (2007-05-01), None
patent: 10-2007-0065033 (2007-06-01), None
Notice of Rejection from Korean Intellectual Property Office dated Apr. 25, 2008.
English Language Abstract of KR 10-2006-0070964.
English Language Abstract of KR 10-2005-0127038.

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