Technique for reconfiguring a high density memory

Details Technique for reconfiguring a high density memory Technique for reconfiguring a high density memory

1996-03-01

1997-11-25

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36518509, G11C 700

Patent

active

056919450

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to manufacturing of integrated circuit memory such as flash EEPROM and the like, and more particularly to techniques for improving the yield in manufacturing of high density memories.
2. Description of Related Art
In the manufacture of high density memories, such as flash EEPROM, designers push the limits of the manufacturing technology. This results in a number of defective devices being produced at any one manufacturing run. The ratio of defective devices to those which work satisfactorily is referred to as manufacturing yield.
Integrated circuit manufacturers use memory redundancy techniques to improve the yield in memory devices. That is, if a particular cell is detected bad, which resides along a particular row or column of the memory, a replacement column or a replacement row can be energized, and the address for the defective row or column redirected to the replacement row or column. This address redirecting preserves the sequential addressing of the data, while replacing a defective cell in the array. However, if there are more defective cells along a given row or column, than can be corrected using the redundancy built in the design, then the memory is bad and cannot be used.
In one prior art U.S. Pat. No. 4,489,401, manufacturing was yield improved by reconfiguring a device having an uncorrectable cell into two halves, where all of the cells in one half have a particular address bit in common. The resulting semiconductor structure will have a memory capacity equal to one half of the original array, and maybe packaged and sold as the smaller device. The technique in the '401 patent involves providing a programmable circuit with an address buffer on the device, which can permanently lock the output of the address buffer into one of the two buffer output states regardless of the address input bit. This makes it possible to isolate and disable every storage cell addressed by that address bit. However, the remaining devices in the array continue to have sequential addresses.
This prior art technique is limited in its application because it requires that no defective cells are found in at least one half of the array. If a defective cell occurs in each half, then device has to be discarded. To retain sequential addressing, this technique requires that only the highest order address bit be manipulated in this way. Otherwise, sophisticated manufacturing techniques which ensure that the address buffers are wired to particular pins on the chip package must be executed to match enabled address buffers with address bus lines.
Accordingly, it is desirable to provide a technique for partitioning a high density memory device to improve yield when defective segments of the array are found. However, the technique should be more flexible than the prior art, allowing for recovery and use of larger number of die in the manufacturing run.


SUMMARY OF THE INVENTION

The present invention provides a flexible technique for improving yield of manufacturing of high density memory devices, such as flash EEPROM. The technique involves configuring an integrated circuit memory array into a plurality of sectors selected by a sector decoder. If defective sectors are detected in the array, it may be partitioned by disabling defective sectors by configuring the sector decoder to prevent access to the defective sectors, while maintaining sequential addressing for remaining sectors in the array. The step of partitioning according to a preferred implementation includes configuring the sector decoder to replace a defective sector in the array identified by N address bits, by another sector in the array having N-m of the N address bits which identify a sector, in common with the defective sector.
Accordingly, in one approach of the present invention the step of partitioning includes configuring the sector decoder to enable a first subset and disable a second subset of the plurality of sectors in the array which have one (m=1) of the N address bits in

REFERENCES:
patent: 5126973 (1992-06-01), Gallia
patent: 5392247 (1995-02-01), Fujita
patent: 5394368 (1995-02-01), Miyamoto
patent: 5481498 (1996-01-01), Han
patent: 5544113 (1996-08-01), Kirihata

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