Testing arrangement for a DRAM with redundancy

Details Testing arrangement for a DRAM with redundancy Testing arrangement for a DRAM with redundancy

1988-03-24

1989-09-12

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 365 51, G11C 700, G11C 2900

Patent

active

048666769

ABSTRACT:
A read/write memory has bit line pairs variously having a first or a second true/complement orientation. Data is selectively coupled to and from the bit line pairs to and from a data line pair via a column decoder. The memory has redundant bit line pairs aligned in the first true/complement arrangement. When a redundant bit line pair is implemented, the logic state of the data is inverted both for reading and for writing if the replaced bit line pair is of the second true/complement orientation. This results in the voltage impressed onto the memory cell for a given logic state is the same for the redundant bit line pair as for the bit line pair that it replaced.

REFERENCES:
patent: 4494220 (1985-01-01), Dumbri et al.
patent: 4692900 (1987-09-01), Ooami et al.

Affiliated with

Also associated with

Rating

Testing arrangement for a DRAM with redundancy does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Testing arrangement for a DRAM with redundancy, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Testing arrangement for a DRAM with redundancy will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-922586