Architecture for a dual-bank page mode memory with redundancy
Architecture with multi-instance redundancy implementation
Architecture, system and method for compressing repair data...
Area efficient global row redundancy scheme for DRAM
Arrangement for the automatic reconfiguration of an intact equip
Arrangement of redundant cell array for semiconductor memory dev
Arrangement with a memory for storing data
Array architecture and operating methods for digital...
Array block level redundancy with steering logic
Array redundancy supporting multiple independent repairs