Semiconductor memory device having hierarchical input/output lin

Semiconductor memory device having improved bit line arrangement

Semiconductor memory device having layout area of periphery of o

Semiconductor memory device having loop configuration

Semiconductor memory device having peripheral circuit and interf

Semiconductor memory device having storage capacity of 2.sup.2N+

Semiconductor memory device having storage node electrodes...

Semiconductor memory device having structure for preventing...

Semiconductor memory device having vertical transistors

Semiconductor memory device including a reference cell

Semiconductor memory device including an SOI substrate

Semiconductor memory device including an SOI substrate

Semiconductor memory device including plurality of memory chips

Semiconductor memory device layout comprising high impurity...

Semiconductor memory device layout comprising high impurity...

Semiconductor memory device obtaining high bandwidth and signal

Semiconductor memory device wired to accommodate increased capac

Semiconductor memory device with bit line pairs crossed at least

Semiconductor memory device with hierarchical bit line...

Semiconductor memory device with low-house pads for electron bea