Semiconductor memory device having loop configuration

Details Semiconductor memory device having loop configuration Semiconductor memory device having loop configuration

1993-09-20

1995-01-03

Limanek, Robert P.

Static information storage and retrieval

Format or disposition of elements

365154, 257903, G11C 700

Patent

active

053792467

ABSTRACT:
A semiconductor memory device includes a plurality of memory cells each specified by selecting one of rows and one of columns, a plurality of word lines to each of which the memory cells associated with selected one of the rows are connected in a branch form, for selecting the rows, and a plurality of bit lines to each of which the memory cells associated with selected one of the columns are connected in a branch form, for selecting the columns and providing data transmission paths for the memory cells, wherein at least one wiring of the word lines and bit lines constitutes part of at least one closed circuit. Thus, even if breaking of wire occurs in part of the wiring in the manufacturing process or in use, the memory device can be prevented from becoming a defective product due to the breaking of wire. As a result, high manufacturing yield and high reliability in use can be obtained.

REFERENCES:
patent: 4872142 (1989-10-01), Hannai
patent: 5008728 (1991-04-01), Yamamura et al.
patent: 5122857 (1992-06-01), Ikeda

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