Semiconductor memory device having vertical transistors

Details Semiconductor memory device having vertical transistors Semiconductor memory device having vertical transistors

2011-05-24

2011-05-24

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Format or disposition of elements

C365S148000, C365S149000, C365S063000, C365S072000

Reexamination Certificate

active

07948784

ABSTRACT:
A semiconductor memory device includes a memory cell array region in which vertical transistors each having a lower electrode connected to a bit line is regularly arranged with a predetermined pitch, including memory cells formed using at least the vertical transistors; a peripheral circuit region arranged adjacent to the memory cell array region in a bit line extending direction; and a predetermined circuit arranged overlapping the peripheral circuit region and the memory cell array region. In the semiconductor memory device, the vertical transistors each having an upper electrode connected to the predetermined circuit are included in an end region of the memory cell array region, in which no word line is provided.

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