Semiconductor memory device having hierarchical input/output lin

Details Semiconductor memory device having hierarchical input/output lin Semiconductor memory device having hierarchical input/output lin

1997-12-10

1999-09-07

Nelms, David

Static information storage and retrieval

Format or disposition of elements

365 63, 36523006, G11C 502

Patent

active

059496975

ABSTRACT:
A semiconductor memory device having a hierarchical input/output line structure and a method for arranging the same are provided. The semiconductor memory device includes a sub-array including a plurality of memory cells. The semiconductor memory device further includes a sense amplifier for sensing and amplifying the data of the memory cells of the sub-array. The semiconductor memory device further includes a sub-word line driver for driving the word lines of the memory cells. The semiconductor memory device further includes a local input/output line for receiving and transmitting the output signal of the sense amplifier. The semiconductor memory device further includes a global input/output line for receiving and transmitting the signal of the local input/output line. The semiconductor memory device further includes switching means for transmitting the signal of the local input/output line to the global input/output line in response to predetermined control signals. A conjunction area is formed in an intersecting area between the sense amplifier and the sub-word line driver. In particular, the switching means are separated and arranged in the conjunction areas in which the local input/output line intersects the global input/output line. A P driver and an N driver for driving the sense amplifier are arranged in the same conjunction.

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"A 2.5ns Clock Access 250MHz 256Mb SDRAM with a Synchronous Mirror Delay," Takanori Saeki, et al., 1996 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 374-375.

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