Semiconductor memory device with hierarchical bit line...

Details Semiconductor memory device with hierarchical bit line... Semiconductor memory device with hierarchical bit line...

1999-11-29

2001-03-06

Nelms, David (Department: 2818)

Static information storage and retrieval

Format or disposition of elements

C365S230030

Reexamination Certificate

active

06198648

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a configuration of a memory cell array and a row decoder in a ROM having a hierarchical bit line architecture.
2. Description of the Related Art
A hierarchical bit line architecture has been proposed for conventional nonvolatile memories, e.g., a FLASH-EEPROM and a mask ROM, (see Japanese Laid-Open Publication No. 6-104406).
FIG. 3A
illustrates part of a layout pattern of a conventional semiconductor memory device having a hierarchical bit line architecture.
FIG. 3B
illustrates part of an equivalent circuit of the conventional semiconductor memory device having a hierarchical bit line architecture shown in FIG.
3
A. The semiconductor memory device having a hierarchical bit line architecture is provided on a semiconductor substrate The semiconductor memory device includes a plurality of main bit lines MB
1
-MB
4
, . . . ; a plurality of sub bit lines SB
11
, . . . , SB
28
, . . . ; a plurality of word lines WL
001
, . . . , WL
232
, . . . ; a plurality of memory cell transistors M
1
-M
7
, . . . (hereinafter referred to as “memory cells”); a plurality of contacts CT
11
, . . . , CT
22
, . . . ; a plurality of auxiliary conductive regions BB
11
, . . . , BB
22
, . . . ; a plurality of bank select transistors TB
01
, . . . , TB
27
, . . . (hereinafter referred to as “bank cells”); and a plurality of bank select lines BS
01
, . . . , BS
24
, . . .
The sub bit lines SB are formed from a diffusion layer of a conductivity type opposite to that of the semiconductor substrate. The word lines WL are provided across the sub bit lines SB and made from polysilicon. Each memory cell M is provided between a pair of adjacent sub bit lines SB. A word line WL is connected to gate electrodes of the memory cells M. Each auxiliary conductive region BB is provided at an end of the sub bit line SB and has the same conductivity type as that of the sub bit line SB. Each bank cell TB is provided between an auxiliary conductive region BB and a sub bit line SB. Each bank select line BS is connected to a gate electrode of a bank cell TB and is made from polysilicon.
The auxiliary conductive regions BB are connected via contacts CT to a main bit line MB. The main bit lines MB are made from a metal. The semiconductor memory device is divided into a plurality of banks BNK
0
-BNK
2
, . . . In each bank BNK, an array of the sub bit lines SB are arranged parallel to each other and a set of the auxiliary conductive regions BB are connected to the sub bit lines SB. A number of the bank select lines BS are provided to a bank BNK. A plurality of the banks BNK are provided along the column direction to form a memory cell array. Adjacent banks BNK share a set of the auxiliary conductive regions BB.
In a bank BNK, the sub bit lines SB are arranged in columns. Of adjacent sub bit lines SB, one sub bit line SB is connected via a bank cell TB to a first main bit line MB at one end of the sub bit line SB while the other sub bit line SB is connected via another bank cell TB to a second main bit line MB at the other end of the other sub bit line SB.
The operation of the semiconductor memory device will be described below. In the following description, it is assumed that the semiconductor substrate is of a P-negative type while the sub bit lines SB and the auxiliary conductive regions BB are of an N-positive type.
A memory cell M is selected by setting potentials of the bank select lines BS and the word lines WL to a high level.
The threshold voltage of the memory cell M can be set by the amount of boron ions which are implanted into a channel region of the memory cell M which is formed under a gate electrode thereof. The threshold voltage of the memory cell M becomes greater through ion implantation. A given amount of implanted ions would produce such a memory cell M that remains in an OFF-state even when a gate potential of the memory cell M is at a high level (OFF-cell). The memory cell M without ion implantation can transition to an ON-state when the gate potential is at a high level (ON-cell).
In a similar way, a portion of the bank select line BS which does not form a bank cell TB is subjected to boron ion implantation so as to be permanently in the OFF-state.
A memory cell M in a bank BNK is selected by a row select circuit
202
driving a word line WL that is connected to a gate electrode of the memory cell M to a high level while driving the associated bank select lines BS that are connected to gate electrodes of the associated bank cells TB connected to the sub bit lines SB which are source and drain regions of the memory cell M to a high level. For instance, the memory cell M
2
shown shaded in
FIGS. 3A and 3B
is read out by selecting the bank cells TB
11
and TB
16
. The bank cells TB
11
and TB
16
are selected by driving the word line WL
132
and the bank select lines BS
11
and BS
14
to a high level and leaving other bit select lines at a low level. When the bank cell TB
11
is selected by the high-level bank select line BS
11
, the sub bit line SB
12
becomes electrically connected via the contact CT
11
to the main bit line MB
2
. When the bank cell TB
16
is selected by the high-level bank select line BS
14
, the sub bit line SB
13
becomes electrically connected via the contact CT
21
to the main bit line MB
1
.
As described above, the memory cell M
2
is selected by activating the word line WL
132
and the bank select lines BS
11
and BS
14
provided on the bank BNK
1
including the memory cell M
2
.
Each of the main bit lines MB are selectively connected to data lines (not shown) by a column select circuit
201
. The data content of the selected memory cell M is read out through a route provided by the connection of the data line and main bit line MB.
The two main bit lines MB
1
and MB
2
are connected via the column select circuit
201
to the data lines. One of the data lines is connected to a low potential while the other of the data lines is connected to a high potential. A state of the memory cell M
2
is read out as binary information by detecting a difference in current between the data lines. When the memory cell M
2
is an OFF-cell, the other data line remains at the high potential. On the other hand, when the memory cell M
2
is an ON-cell, the other data line makes a transition from a high to a low potential. The presence of a transition determines the binary information of the memory cell M
2
.
By introducing a hierarchical bit line architecture to the memory, the following effect is obtained. Of the plurality of the sub bit lines SB connected to one main bit line MB, only the sub bit lines SB connected to one memory cell M which is a target to be accessed are selected by the bank select lines BS. As a result, a load of the main bit line MB is reduced, thereby realizing high-speed access.
In the above-described nonvolatile memory, a single memory cell M includes one transistor, so that a density of memory cells M is high compared with that of a volatile memory such as a DRAM. However, the wiring pitch of the word lines WL is very small and therefore it is difficult to provide a row decoder and a driving circuit for each word line WL. To solve this problem, a plurality of banks BNK share a group of row decoders and driving circuits. In other words, consecutive plural banks BNK are connected to the same group of row decoders and driving circuits via a common group of word lines WL. Accordingly, the word lines WL each corresponding to an identical row in each of the consecutive plural banks BNK are provided with the same signal and activated simultaneously. To read out an intended memory cell M, it is necessary to activate the bank select lines BS in the bank BNK including the intended memory cell M of the plural banks BNK so as to connect the main bit lines MB to the intended memory cell.
FIG. 3C
illustrates a configuration of a conventional semiconductor memory device. Memory cell arrays
11
and
12
are provided on opposite sides of the row

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