Semiconductor memory device wired to accommodate increased capac

Details Semiconductor memory device wired to accommodate increased capac Semiconductor memory device wired to accommodate increased capac

1991-05-22

1993-03-16

Dixon, Joseph L.

Static information storage and retrieval

Format or disposition of elements

365 63, 257734, G11C 506

Patent

active

051950537

ABSTRACT:
A boundary region for wiring is provided by expanding one of a plurality of boundary regions boundary regions each being between adjacent ones of a plurality of decoder circuits included in a decoder circuit block corresponding to a memory cell array by shifting a desired portion of at least one of the decoder circuits by a desired distance and a wiring connecting wirings in the decoder circuit to a circuit provided outside the decoder circuit block is arranged in the boundary region for wiring, so that a circuit arrangement in a second region outside the decoder circuits can be made freely.

REFERENCES:
patent: 4695978 (1987-10-01), Itakura
patent: 4779227 (1989-10-01), Kurafuji et al.
patent: 4849943 (1989-07-01), Pfennings
patent: 4896302 (1990-01-01), Sato et al.
patent: 5007025 (1991-04-01), Hwang et al.
patent: 5097440 (1992-03-01), Konishi et al.
patent: 5103282 (1992-04-01), Isomura et al.
IEEE Journal of Solid-State Circuits, vol. 17, No. 3, Jun. 1982, New York US, pp. 459-464; Anceau et al., "Complex Integrated Circuit Design Strategy".
"Principles of CMOS VLSI Design", Oct. 1985, Addison-Wesley, Reading, US, pp. 205-211, Weste et al, "Pseudo 2-phase Memory Structures".

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