Processor controlled command port architecture for flash memory

Details Processor controlled command port architecture for flash memory Processor controlled command port architecture for flash memory

1990-10-19

1993-06-22

Kriess, Kevin A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365218, 395425, 364DIG2, 364965, 364933, 3649335, 36493361, G11C 800

Patent

active

052220460

ABSTRACT:
A semiconductor flash EPROM/EEPROM device which includes a command port controller for receiving command instructions from a data bus coupled to the memory device. Instruction words to a command port controller operates to instruct the device to perform read, erase, program, or verify functions and the command port controller generates necessary control signals to cause the memory to function appropriately. By utilizing the command port controller the memory device can be erased and programmed while the device is in the circuit and permits pin compatibility with the prior art EPROM and EEPROMs.

REFERENCES:
patent: 4412309 (1983-10-01), Kuo
patent: 4460972 (1984-07-01), Homan et al.
patent: 4460982 (1984-07-01), Gee et al.
patent: 4752871 (1988-06-01), Sparks et al.
patent: 4763305 (1988-08-01), Kuo
patent: 4783764 (1988-11-01), Tsuchiya et al.
patent: 4811294 (1989-03-01), Kobayashi et al.
patent: 4970692 (1990-11-01), Ali et al.
patent: 5034922 (1991-07-01), BurgessG351 1
V. N. Kynett, A. Baker, M. Fandrich, G. Hoekstra, O. Jungroth, J. Kreifels, and S. Wells, An In-System Reprogrammable 256K CMOS Flash Memory, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 132-133 Feb. 17-19, 1988).
L. Gee, P. Cheng, Y. Bobra, and R. Mehta, An Enhanced 16K EEPROM, IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, pp. 828-832 Oct. 1982).
S. Grosman, M. Knecht, N. Challa, 64K CMOS EEPROM Sheds System Overhead, Electronic Design, pp. 133-138, (Dec. 8, 1983).
French Patent Office Search Report.

Affiliated with

Also associated with

Rating

Processor controlled command port architecture for flash memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Processor controlled command port architecture for flash memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor controlled command port architecture for flash memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1444869