Path gate driver circuit

Details Path gate driver circuit Path gate driver circuit

2002-09-12

2004-04-27

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189050, C365S189110

Reexamination Certificate

active

06728160

ABSTRACT:

FIELD OF THE INVENTION
Embodiments of the present invention relate to memory devices, and more particularly to memory device decoder circuits.
BACKGROUND OF THE INVENTION
Prior art
FIG. 1
, is a diagram of a memory device with an associated decoder circuit. As depicted in
FIG. 1
, the memory device comprises a plurality of memory cells (MC)
110
arranged in rows and columns. The memory cells in a row share a common wordline
120
connection; while memory cells in a column share a common bitline
130
connection. Signals are applied to the word line and bit line to selectively read, write, and erase one or more desired memory cells in the array.
A decoder circuit is connected to each bitline. For purposes of clarity, however, only a single decoder circuit connected to a single bitline is shown. The decoder circuit may include a decoder circuit, which comprises a path gate
140
coupling the bit line
130
to a sense amplifier
150
. The sense amplifier
150
detects a signal on the bitline and outputs a signal, indicative of the programming state of the selected memory cell, to a data buffer
160
.
As semiconductor memory technology progresses, increasing read margins becomes critical. Increasing read margins can be achieved by reducing voltage losses across the read circuit.
Currently, one or more path gates
140
are utilized in the decoder circuitry of memory devices. The path gate is used to selectively couple a bitline to a sense amplifier. The path gate is typically a metal oxide silicon field effect transistor (MOSFET), having a gate (G), a drain (D) and a source (S) terminal. When the path gate
140
is off, there is no conducting channel between the source and drain terminals. When the path gate
140
is on, a conducting channel, having a small resistance, is induced. Thus, the path gate
140
introduces a signal loss on the selected bitline
130
.
The channel resistance can be reduced, and the read margin increased, by utilizing a boosted control signal. The boosted control signal is approximately two or three times the supply voltage (Vcc) in the high state, and approximately 0V in the low state. The boosted control signal is coupled to the gate terminal of the path gate. The increased gate voltage acts to reduce the channel resistance across the path gate (i.e. between the drain and source terminals).
The boosted control signal is provided by a path gate driver circuit
170
(hereinafter referred to a driver circuit). Referring now
FIG. 2
, a diagram of a driver circuit
170
in accordance with the prior art is shown. The driver circuit
170
typically has an output stage comprising a pair of transistors. A first transistor
210
provides a pull-up to a boost-high supply (6.5V). A second transistor
220
provides a pull-down to a boost-low supply (ground). When the control signal is in a low state (0V), the pull-down transistor
220
of the output stage is off, and the pull-up transistor
210
of the output stage is on. Therefore, the output of the driver circuit is high (6.5V). When the control signal switches to a high state (3V), the pull-down transistor
220
of the output stage turns on. However, the pull-up transistor
210
does not turn completely off, because the control signal (3V) is less than the boost-high voltage (6.5V). Therefore, the pull-down transistor
220
has to sink the current flowing in the pull-up transistor
210
. The current results in a voltage drop across the channel resistance of the pull-down transistor
220
. Thus, the output stage of the current driver circuit cannot provide a boost-low output voltage of 0V. The introduced voltage drop across the channel resistance results in a low output voltage of approximately 2V-3V. Furthermore, the low output voltage level (2V-3V) is greater than the threshold voltage of the path gate transistor. Therefore, the path gate transistor
140
will not be completely turned off. The resulting current flow increases the power consumption in the decoder circuit.
The channel resistance in the pull-down transistor
220
of the driver circuit
170
also affects the switching time constant of the path gate
140
. The channel resistance of the output stage affects the time constant associated with discharging the path gate's
140
gate capacitance. The higher the channel resistance of the output stage of the driver circuit
170
, the longer it takes to discharge the gate capacitance of the path gate
140
.
Thus, the prior art suffers from the fact that the pull-up of the output stage of the path gate driver circuit does not completely turn off. The prior art is therefore disadvantageous in that the boosted control signal is not substantially 0V when in a low state. As a result, the prior art is disadvantageous because of the path gate resistance. The prior art is also disadvantageous because of the path gate switching time.
SUMMARY OF THE INVENTION
An improved driver circuit is disclosed. In one embodiment, the driver circuit includes a shunt stage, a level shifter stage, a pull-up stage, and an output stage. The shunt stage has a control terminal coupled to a supply, and an input terminal coupled to a control signal path. The level shifter stage has a first control terminal coupled to the control signal path, a second control terminal coupled to an output terminal of the shunt stage, a first input terminal coupled to a boost-low supply, and a second input terminal coupled to a boost-high supply. The pull-up stage has a control terminal coupled to an output terminal of the level shifter stage, and an input terminal coupled to the boost-high supply. The output stage has a first control terminal coupled to the output terminal of the shunt stage and an output terminal of the pull-up stage, a second control terminal coupled to the control signal path, a first input terminal coupled to the boost-low supply, and a second input terminal coupled to the boost-high supply. A boosted control signal is thereby provided at the output terminal of the output stage in response to the control signal.


REFERENCES:
patent: 5202855 (1993-04-01), Morton
patent: 5646898 (1997-07-01), Manning
patent: 6330196 (2001-12-01), Protzman

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