Predecode column architecture and method

Details Predecode column architecture and method Predecode column architecture and method

2003-08-18

2004-08-03

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189050, C365S230080, C365S230090

Reexamination Certificate

active

06771557

ABSTRACT:

TECHNICAL FIELD
This invention relates to memory devices capable of operating in a burst mode, and, more particularly, to a column address path for burst mode memory devices provide more optimum propagation of column addresses.
BACKGROUND OF THE INVENTION
Memory devices, including a synchronous dynamic random access memory (SDRAM)
10
shown in
FIG. 1
, typically receive both a row address and a column address that specify where data are to be transferred to or from within the memory device. The row and column addresses are initially applied to an address register
12
through an address bus
14
. The address bus
14
is generally coupled to a memory controller (not shown in FIG.
1
). Typically, a row address is initially received by the address register
12
and applied to a row address multiplexer
18
. The row address multiplexer
18
couples the row address to a number of components associated with either of two memory banks
20
,
22
depending upon the state of a bank address bit forming part of the row address. Associated with each of the memory banks
20
,
22
is a respective row address latch
26
that stores the row address, and a row decoder
28
that applies various signals to its respective array
20
or
22
as a function of the stored row address. The row address multiplexer
18
also couples row addresses to the row address latches
26
for the purpose of refreshing the memory cells in the arrays
20
,
22
. The row addresses are generated for refresh purposes by a refresh counter
30
that is controlled by a refresh controller
32
.
After the row address has been applied to the address register
12
and stored in one of the row address latches
26
, a column address is applied to the address register
12
. The address register
12
couples the column address to a column address latch
40
. In a normal operating mode, the column address is coupled through a burst controller
42
directly to an address buffer
44
. However, in a burst operating mode, the burst controller
42
generates a sequence of column addresses starting at the column address applied to the burst controller
42
from the column address latch
40
. For example, the burst controller
42
may operate in a “burst
2
” mode, in which one additional column address is generated by the burst controller
42
, a “burst
4
” mode, in which three additional column addresses are generated by the burst controller
42
, and a “burst
8
” mode, in which seven additional column addresses are generated by the burst controller
42
. The burst controller
42
may also operate in either of two burst modes, namely a serial mode, in which the addresses generated by the burst controller
42
are sequential, or an interleaved mode, in which the addresses generated by the burst controller are sequential except that only the least significant bit (LSB) toggles between each pair of even and odd addresses. As discussed in greater detail below, it is important that column addresses generated by the burst controller
42
be quickly coupled to the column address buffer
44
after the burst controller
42
receives the initial column address from the column address latch
40
.
After the burst controller
42
applies a column address to the column address buffer
44
in either the normal mode or the burst mode, the column address buffer
44
applies the column address to a column decoder
48
. As is well known in the art, the column decoder
48
applies various signals to respective sense amplifiers and associated column circuitry
50
,
52
for the respective arrays
20
,
22
.
Data to be read from one of the arrays
20
,
22
is coupled to the column circuitry
50
,
52
for the arrays
20
,
22
, respectively. The data are then coupled to a data output register
56
, which applies the data to a data bus
58
. Data to be written to one of the arrays
20
,
22
are coupled from the data bus
58
through a data input register
60
to the column circuitry
50
,
52
where they are transferred to the arrays
20
,
22
, respectively. A mask register
64
may be used to selectively alter the flow of data into and out of the column circuitry
50
,
52
, such as by selectively masking data to be read from the arrays
20
,
22
.
The above-described operation of the SDRAM
10
is controlled by a command decoder
68
responsive to high-level command signals received on a control bus
70
. These high level command signals, which are typically generated by a memory controller (not shown in FIG.
1
), are a clock enable signal CKE*, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, which the “*” designating the signal as active low. The command decoder
68
generates a sequence of control signals responsive to the command signals to carry out the function (e.g., a read or a write) designated by the command signals. These control signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted. The high-level command signals are clocked into the command decoder
68
in synchronism with a clock signal CLK. The CLK signal, or internal clock signals (not shown) generated from the CLK signal, control the timing at which the control signals carry out their respective functions in the SDRAM
10
. The control signals are preferably registered with both the rising and falling edges of the CLK signal (or internal clock signals) so that two operations are accomplished each period of the CLK signal. An SDRAM
10
operating in this manner is known as a “double data rate DRAM” because two bits of data are read from or written to the SDRAM
10
for each clock CLK pulse.
One conventional design for a portion of the burst controller
42
is illustrated in FIG.
2
. The burst controller
42
′ may include substantially more circuitry than is shown in
FIG. 2
, but this circuitry has been omitted in the interest of brevity because this additional circuitry is not particularly relevant to the problem that the disclosed invention is intended to solve. External column address signals XA
9
-XA
0
(or XA<
9
:
0
>) are coupled to the SDRAM
10
through the address bus
14
(
FIG. 1
) and then through the address register
12
to the column address latch
40
. As previously mentioned, the burst controller
42
′ then outputs column address designated as IA<
9
:
0
> to the column address buffer
44
. In the burst mode, bits IA<
0
> and IA<
9
:
3
> of the internal column address are generated differently from the remaining bits IA<
1
> and IA<
2
> of the internal column address. More specifically, the IA<
0
> and IA<
9
:
3
> bits are generated by coupling the external bits A<
0
> and A<
9
:
3
> from respective column address latches
40
through a respective column address path
90
. The reason these bits are generated differently is that the maximum size of the burst is 8 bits, and 8 bits can be counted using three bits of the internal address, i.e., IA<
2
:
0
>. The bits IA<
9
:
3
> of the internal column address are constant as the IA<
2
:
0
> bits are incremented by a count of either 2, 4 or 8, depending upon the length of the burst. The IA<
0
> bit selects whether an even or an odd-numbered column will be initially addressed, and it toggles with each edge of the CLK signal, assuming the SDRAM
10
is a double data rate SDRAM.
As mentioned above, in the burst mode, the IA<
2
> and IA<
1
> bits are incremented from their initial values for even column addresses under certain conditions. This incrementing is accomplished for the column address bits of the burst by adder logic circuits
100
and
102
. Latched external address bits LA_S
1
and LA_S
2
are applied to an input of a respective multiplexer
110
,
112
. The other input of each multiplexer receives a respective set of bits from a burst counter
116
. The burst counter
116
supplies the

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