Programmable address logic for solid state diode-based memory

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

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Details

C365S105000, C365S103000, C365S096000, C365S189080

Reexamination Certificate

active

06587394

ABSTRACT:

BACKGROUND
The present invention relates to information storage devices. More specifically, the present invention relates to one-time programmable (OTP) solid state memory.
Portable devices such as PDAs, handheld computers, digital cameras and digital music players include memory for storing data, digital images and MP3 files. Different types of memory are available for these portable devices. Conventional memory types include flash memory, mini-hard drives, mini-compact discs, and magnetic tape. However, each of these memory types has one or more of the following limitations: large physical size, low storage capacity, relatively high cost, poor robustness, slow access time and high power consumption.
A solid state diode-based OTP memory is disclosed in assignee's U.S. Ser. No. 09/875,356 filed Jun. 5, 2001. Compared to the conventional memory, the diode-based memory has a high shock tolerance, low power consumption, fast access time, moderate transfer rate and good storage capacity. The diode-based memory can fit into a standard portable interface (e.g., PCMCIA, CF) of a portable device.
Address logic of the diode-based memory device is formed on the same level as main memory. In a multi-level diode-based memory device, each level has main memory and address logic (unlike conventional solid state memory such as DRAM). Moreover, the address logic of the diode-based memory device is programmable. The address logic may be programmed after each layer has been fabricated. Since no masking is required, physical processing is simplified.
SUMMARY
According to one aspect of the present invention, a solid state memory device includes a decoder having first and second groups of address elements, the address elements of the first group having been assigned a first logic value and the address elements of the second group having been assigned a second logic value. Current-carrying capability of the first group of address elements is greater than current-carrying capability of the second group of address elements. Current flowing through the address elements during programming causes the resistance states of only the second group of address elements to change.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.


REFERENCES:
patent: 3384879 (1968-05-01), Stahl et al.
patent: 3656120 (1972-04-01), Maure
patent: 4287569 (1981-09-01), Fukushima
patent: 5889694 (1999-03-01), Shepard
patent: 6373742 (2002-04-01), Kurihara et al.

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