Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2001-12-28
2004-03-09
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S194000
Reexamination Certificate
active
06704240
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a predecoder; and, more particularly, to a predecoder capable of preventing an error of column addresses generated by overlapping of predecoder addresses.
DESCRIPTION OF THE PRIOR ART
Recently, a memory device requires not only a low-power consumption and a high-speed performance, but also a stable characteristic thereof. However, as a frequency is increased, there are limitations for a stable operation of the memory device and for a timing margin of internal logics.
FIG. 1
is a block diagram showing a path for outputting column address in semiconductor memory device according to the prior art.
Referring to
FIG. 1
, an address signal (add) inputted through an address buffer
11
and a column address strobe signal (cas
1
) inputted through a command signal buffer
13
are synchronized with an internal clock signal (clkt
4
) inputted through a clock buffer
12
in a latch
14
and a command signal decoder
15
respectively. Address signals a<0:6> and ab<0:6> passing through the latch
14
are inputted into a first, second, and third predecoders
18
,
19
and
20
. A counter
16
, in which address signals a<0:1> are inputted, outputs counting signals (ay_int<0:6>) and the counting signals (ay_int<0:6>) are inputted into the first, second and third predecoders
18
,
19
and
20
. The command signal decoder
15
outputs a read/write signal (casatv
6
) and a signal corresponding to a burst length determined by the read/write signal (casatv
6
) and those are inputted into a predecoders control circuit
17
. The predecoder control circuit
17
receives the read/write signal (casatv
6
) the signal corresponding to a burst length, a plurality control signals (ybnd_ypc and term_ypc) and the internal clock signal (clk
4
) and outputs a first and second predecoder control signals (ypce_p and ypci_p) and a first and second predecoder level signals (ypce_l and ypci_1) and these signals outputted from the predecoder control circuit
17
are inputted into the first, second and third predecoder
18
,
19
and
20
. The first predecoder
18
receives the first and second control signals (ypce_p and ypci_p), the address signals (a<0:1> and ab<0:1>), which represent address signals from 0 to 1, and the counting signals (ay_int<0:1>), which represent counting signals form 0 to 1, and outputs first predecoder signals (gy
01
<0:3>). The second predecoder
19
receives the first and second predecoder level signals (ypce_l and ypci_l), the address signals (a<2:3> and ab<2:3>) and the counting signals (ay_int<2:3>) and outputs second predecoder signals (gy
23
<0:3>). The third predecoder
20
receives the first and second predecoder level signals (ypce_l and ypci_l), the address signals (a<4:6> and ab<4:6>) and the counting signals (ay_int<4:6>) and outputs third predecoder signals (gy
456
<0:7>). A decoder
21
receiving the output signals of the first, second and third predecoders
18
,
19
and
20
outputs column address signals (yi<0:3>).
As shown in the above layout, the predecoder has been used to reduce the number of transistors in outputting the column address signal. At this time, the address signals are grouped to some of address signals and the number of cases capable of grouping address signals is calculated. In the SDRAM, address signals, which are applied from an external circuit, are changed into internal address signals by a counter and then a burst operation of the internal address signals is performed. Address
0
and address
1
signals are grouped so that a signal of pulse type is generated in the first predecoder and addresses
2
and
3
signals, addresses
3
and
4
signals and addresses
5
and
6
signals are changed into signals of a level type in the second and third predecoder. The signals of pulse type and the signals of level type are used as predecoder signals.
FIG. 2
is a circuit diagram showing a decoder according to the prior art. A dynamic is used to reduce an area of decoder.
Referring to
FIG. 2
, the first predecoder signals (gy
01
<0:3>) are inputted with an identical address input path into each decoder. Now, an input path of address
0
signal (<0>) will be, for example, described.
A first PMOS transistor P
11
, which is driven in response to the address
0
signal, is connected to a power supply voltage VDD terminal and a first node Q
11
. A first NMOS transistor N
11
, which is driven in response to the address
0
signal (gy
01
<0>) of the first predecoder
18
, is connected between the first node Q
11
and a ground voltage VSS terminal. A fifth NMOS transistor N
15
driven in response to the address
0
signal (gy
23
<0>) of the second predecoder
19
and a sixth NMOS transistor driven in response to the address
0
signal (gy
456
<0>) of the third predecoder
20
are connected in series. A second PMOS transistor P
12
, which is driven in response to an output signal of an inverter I
11
, is connected to the supply voltage VDD terminal and the first node Q
11
. A potential of the first node Q
11
is inverted and delayed in passing through the first, second and third inverters I
11
, I
12
and I
13
and column address signals (yi<0:3>) are outputted.
In order to drive the above decoder, the fifth and sixth NMOS transistors N
15
and N
16
are turned on at the same time. The address
2
,
3
,
4
,
5
, and
6
signals have to be inputted in the decoder in advance for the address signals to perform a burst operation. The address
0
and
1
signals are inputted with a pulse type and the address
2
and
3
signals and the address
4
,
5
and
6
signals are inputted with a level type such as the prior art. The signal of level type is transited one time so that a current consumption is low, however, a large margin is required. It is disadvantageous for a time to access a column address.
FIG. 3
is a timing diagram showing a read interrupt according to the prior art.
Referring to
FIG. 3
, when the address
1
signal (gy
23
<1>) of the second predecoder is enabled, the address
0
signal (gy
23
<0>) has to be disabled; however, two address signals (gy
23
<1> and gy
23
<0>) may be overlapped so that two column address signals may be outputted. As shown in
FIG. 3
, the column address
1
signal (yi<1>) and the column address
5
signal (yi<5>) are outputted at the same time. To prevent the above problem, an enable time of the predecoded address signal has to be delayed to secure an enough margin; however, an access time loss of column address signal is generated.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a predecoder control circuit, which can prevent an error of column address signals generated by overlapping of predecoder address signals and secure an enough margin without an access time loss of column address signals.
In accordance with an aspect of the present invention, there is provided a predecoder control circuit comprising: a first inversion delay means for inverting and delaying a first control signal as much as a predetermined time; a first latch means for determining potential of a first node by inverting and latching an output signal of the first inversion delay means; a second inversion delay means for inverting and delaying the potential of the first node; a third inversion delay means for logically combining a second control signal and a third control signal and delaying the logically combined signal as much as a predetermined time; a second latch means for determining potential of a second node by inverting and latching an output signal of the third inversion delay means; a fourth inversion delay means for inverting and delaying potential of the second node; a switching means for adjusting potential of a third node in response to a fourth control signal and a clock signal; a third latch means for latching potential of the third node; a first logic means for logi
Hynix / Semiconductor Inc.
Le Vu A.
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