Configurable SRAM for field programmable gate array

Details Configurable SRAM for field programmable gate array Configurable SRAM for field programmable gate array

1998-02-23

1999-03-16

Nelms, David

Static information storage and retrieval

Addressing

Multiple port access

36523002, 36518902, G11C 800, G11C 1604

Patent

active

058838520

ABSTRACT:
A configurable SRAM for a field programmable gate array. Two memory arrays each have a data input, a data output, a write enable input and port A and B address inputs. First and second address buses are selectively coupled to the port A and port B address inputs through multiplexers such that different configurations can be achieved. The multiplexers are controlled by a dual port/single port steering signal and a x1/x2 steering signal such that the following configurations can be achieved: 32 x1 dual port; 32 x1 single port and 16 x2 single port. In dual port configurations, simultaneous read and write operations to different cells can occur. In x2 configuration, each array is operated as an independent memory with its own address input, its own data output and its own data input. In x1 single port configuration, one data input line and one data output line and one address bus are shared between the two arrays, and an extra address bit is used to steer the write enable signals and the output multiplexer circuitry such the write enable signal reaches the proper array and the data output from the array being read reaches the shared output line.

REFERENCES:
patent: 5500609 (1996-03-01), Kean
patent: 5563829 (1996-10-01), Huang
patent: 5614844 (1997-03-01), Sasaki et al.

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