CMOS memory cell

Details CMOS memory cell CMOS memory cell

1991-09-16

1993-06-01

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Multiple port access

36518904, G11C 1300

Patent

active

052166368

ABSTRACT:
A dual port random access memory cell is coupled to complementary read/write data bit lines, a read-only data bit line, a read/write address line and a read-only address line. The memory cell includes two two-transistor inverters (36, 38) cross-coupled to form a flip-flop core memory which is coupled to complementary input/output nodes (40, 42). A fifth transistor (44 or 56) has its main electrodes connected between the first input/output node (40) and the first read/write data bit line (BLA) and its gate electrode connected to the read/write address line (ROW SELA or ROW SELA). The sixth transistor (46 or 58) has its main electrodes connected between the second input/output node (42) and the second read/write data bit line (BLA) and its gate electrode connected to the read/write address line (ROW SELA or ROW SELA). A seventh transistor (48) has its main electrodes connected between an upper power supply potential (VCC) and a common node (54) and has its gate electrode connected to the second input/output node (42). An eighth transistor (50 ) has its main electrodes connected between the common node (54) and a lower power supply potential (VSS) and its gate electrode connected to the first input/output node (40). A ninth transistor (52) has its main electrodes connected between the common node (54) and the read-only date bit line (BLB) and its gate electrode connected to the read-only address line (ROW SELB).

REFERENCES:
patent: 4768172 (1988-08-01), Sasaki
patent: 4858190 (1989-08-01), Yamaguchi et al.
patent: 4933899 (1990-06-01), Gibbs
patent: 5023844 (1991-06-01), Arnold et al.

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