Combination dual-port random access memory and multiple first-in

Details Combination dual-port random access memory and multiple first-in Combination dual-port random access memory and multiple first-in

1995-09-08

1996-10-22

Nelms, David C.

Static information storage and retrieval

Addressing

Multiple port access

36518902, 36518905, 36523008, G11C 800, G11C 700

Patent

active

055684432

ABSTRACT:
A data processor memory system that combines in a single memory array, a plurality of first-in-first-out (FIFO) buffer memories and a dual-port random access read-write memory (RAM). The memory array is divided into one region for the FIFO buffers and another region for the RAM memory. The memory system reads and writes data to the RAM region independently of the FIFO buffer region. The system enables access to the RAM memory by signals addressed to address fields within the RAM region, and enables access to the FIFO buffer memories by signals addressed to address fields within the FIFO region. The system writes data to each of the FIFO buffer memories utilizing an associated write pointer, and increments each write pointer when data is written to its associated FIFO buffer memory. The system reads data from each of the FIFO buffer memories utilizing an associated read pointer, and increments the read pointer when data is read from its associated FIFO buffer memory. The write pointers and the read pointers roll-over to a first address in their associated FIFO buffers when each pointer reaches the top of addressable memory in its associated FIFO buffer memory.

REFERENCES:
patent: 5406554 (1995-04-01), Parry

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