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Single poly-emitter PNP using DWELL diffusion in a BiCMOS...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single poly-Si process for DRAM by deep N well (NW) plate

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single polysilicon process for DRAM

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single sided buried strap

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single transistor RAM cell and method of manufacture

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single transistor vertical memory gain cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single transistor vertical memory gain cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single wafer thermal CVD processes for hemispherical grained...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single wafer thermal CVD processes for hemispherical grained...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single-chip contact-less read-only memory (ROM) device and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single-electron device including therein nanocrystals

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single-pole component manufacturing

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single-poly EPROM and method for forming the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single-side corrugated cylindrical capacitor structure of high d

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Smart grading implant with diffusion retarding implant for...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Smart grading implant with diffusion retarding implant for...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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SOI body contact using E-DRAM technology

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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SOI bottom pre-doping merged e-SiGe for poly height reduction

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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SOI device with charging protection and methods of making same

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SOI device with different crystallographic orientations

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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