Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-01-22
2008-01-22
Sarkar, Asok Kumar (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S162000, C257SE21343
Reexamination Certificate
active
11086498
ABSTRACT:
A method of making an integrated circuit chip is provided, which combines a smart grading implant with a diffusion retarding implant, e.g., to improve short channel effect controllability and improve dopant grading in the source/drain regions. Using a smart grading implant, a relatively low-energy high-dose implant is performed before a relatively low-energy high-dose implant. Hence, a relatively high-energy low-dose implant of ions is performed into a source/drain region of a substrate. A diffusion retarding implant is performed into the source/drain region of the substrate. Then after performing the high-energy low-dose implant and the diffusion retarding implant (together, overlapping, or separately), a relatively low-energy high-dose implant of ions is performed into the source/drain region of the substrate.
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Wang Chih-Hao
Wang Ta-Wei
Sarkar Asok Kumar
Slater & Masil, L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
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