Gated clock recovery circuit
Generating a clock crossing signal based on clock ratios
Generating non-integer clock division
Generation of phase shifted clock using selected multi-level ref
Generator for delay-matched clock and data signals
Glitch free clock start/stop control circuit for outputting a si
Glitch-free phase switching synthesizer
Glitchless clock switch circuit
GM cell based control loops
GM cell based control loops
Half synchronizer circuit interface system
Half-rate clock and data recovery circuit
Half-rate clock and data recovery circuit
Half-rate phase detector with reduced timing requirements
Header synchronization detector
Hierarchical synchronization method
Hierarchical synchronization method
Hierarchical synchronization method and a telecommunications sys
High bit rate start code searching and detecting circuit and met
High frequency all digital phase-locked loop