High frequency all digital phase-locked loop

Details High frequency all digital phase-locked loop High frequency all digital phase-locked loop

1997-03-13

1999-10-26

Ghebretinsae, Temesghen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327158, 331 1A, H03D 324, H03L 706, H03L 700

Patent

active

059741058

ABSTRACT:
An improved high-frequency all-digital phase-locked loop for locking a local signal in phase with an input signal is disclosed. It contains a novel digital control oscillator which includes: (a) a delay line comprising L delay gates for generating L clocks, where L is an integer and each of the delay gates has a delay time .PHI.; (b) a programmable up-down N-counter, where N is an integer; (c) a multiplexer which selects one of the L clocks based on a count of the up-down N-counter programmable; and (d) an adaptive-compensative circuit for determining the value of N based on the following conditions: ##EQU1## The adaptive-compensative circuit is implemented with a boolean encoder. This improved design allows all-digital PLL's to be constructed without a high frequency system clock, while, at the same time, maintains excellent stability and generates minimum output jitters.

REFERENCES:
patent: 4789996 (1988-12-01), Butcher
patent: 5488641 (1996-01-01), Ozkan
Loau et al, "PHDPLL for Sonet Desynchronizer", IEEE, 1991.

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