Generation of phase shifted clock using selected multi-level ref

Details Generation of phase shifted clock using selected multi-level ref Generation of phase shifted clock using selected multi-level ref

1992-08-12

1998-10-06

Bocure, Tesfaldey

Pulse or digital communications

Synchronizers

Frequency or phase control using synchronizing signal

331 45, 363148, H04B 1500

Patent

active

058188894

ABSTRACT:
A phase shifter system includes a number of gates 40, 41 for receiving a reference clock and a number of gates 30-33 for receiving a predicted desired phase. The reference clock is manipulated by latches 43-46 and further gates 48, 49 so as to produce quadrature derivatives and these are connected across the resistor chain R1-R9 to produce multilevel waveforms, the steps being selected by selector 36 connected to the resistor nodes under the control of the predicted phase information from gates 30-33. Filtering and reshaping via comparator 50 provides an output clock pulse of desired phase. The output clock can be used to provide phase control in a transmission/reception system on a communications network.

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EPO Search report.

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