Generating non-integer clock division

Details Generating non-integer clock division Generating non-integer clock division

2005-10-18

2005-10-18

Bocure, Tesfaldet (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S115000

Reexamination Certificate

active

06956922

ABSTRACT:
A clock divider and method is disclosed for generating an output clock signal having a frequency that is a fractional or integral multiple of a reference clock signal frequency. In one embodiment, the clock divider divides a clock signal by a first divisor in a first period and by a second divisor in a second period, where the second period following the first period. The clock divider circuit is triggered by a first edge of the clock signal and generates a first signal. A synchronizing circuit is coupled to the clock divider to generate a second signal from the first signal, the second signal being synchronized by a second edge of the clock signal, where the second edge is in a direction opposite to the first edge. A selector is coupled to the synchronizing circuit and the clock divider to generate an output signal by selecting the first signal and the second signal alternately between the first period and the second period.

REFERENCES:
patent: 5389826 (1995-02-01), Sonobe
patent: 6041093 (2000-03-01), Cho
patent: 6061418 (2000-05-01), Hassoun
patent: 6121801 (2000-09-01), Lee
patent: 6356123 (2002-03-01), Lee et al.
patent: 6489817 (2002-12-01), Wong et al.

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