Pulse or digital communications – Synchronizers
Reexamination Certificate
2005-12-21
2009-12-01
Ghayour, Mohammad H (Department: 2611)
Pulse or digital communications
Synchronizers
Reexamination Certificate
active
07627065
ABSTRACT:
A multiple clock domain system. A system comprises two clock domains which receive a source clock signal. The first domain includes a first clock signal with a first frequency and the second domain includes a second clock signal with a second frequency. A ratio of the first frequency to the second frequency is N:M. The first domain is configured to initialize a count to N, if N is less than 2*M; and initialize the count to M, if N is not less than 2*M. Subsequently, on each cycle of the first clock signal, the first domain adds (M-N) to the count and asserts a sample enable signal, if the count is greater than or equal to N; and adds a value equal to M to the count and negates the sample enable signal, if the count is not greater than or equal to N.
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Daga Bharat K.
Schulz Jurgen M.
Ghayour Mohammad H
Meyertons Hood Kivlin Kowert & Goetzek, P.C.
Panwalkar Vineeta S
Rankin Rory D.
Sun Microsystems Inc.
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