Glitchless clock switch circuit

Pulse or digital communications – Synchronizers

Reexamination Certificate

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Details

C713S501000

Reexamination Certificate

active

06275546

ABSTRACT:

The present invention generally relates to digital electronic circuitry, and more particularly to a switching circuit for switching between two separate input clock signals for producing an output clock signal that is synchronized to one of the input clock signals.
It is common in computer networking environments, as well as other environments where data is transferred between devices that different clock signals are used to control the communication during transmitting and receiving modes of operation. This is the case, for example, when communicating between a personal computer (PC) and a networking device, where the networking device has its own clock signal and the PC would have a clock signal for its data, so that when data comes into the PC, two separate clocks would be present. One clock would be used to transmit data out and the other would be used to receive the data. There are other similar situations where it is necessary to switch between two free-running input clock signals, which may be at the same frequency or at a different frequency and/or phase. It is important that the switching is done in a manner which does not disrupt the operation or integrity of the communication of the data that is being transferred.
A common problem that is associated with the switching from one clock to another is that a clock pulse width at or near the switching operation will be shrunk, i.e., it will be less than the fall clock pulse width or period. For high frequency clock signals, the narrower pulse width, which may be characterized as a sliver may not be capable of being detected by a storage device, for example, and some disruption of accurate communication can easily result. The producing of such narrower than standard pulse widths or shorter clock periods are defined herein as being glitches.
Accordingly, it is a primary object of the present invention to provide an improved clock switching apparatus which prevents glitches in the resulting output clock signal.
Another object is to provide such an improved apparatus which reliably operates to switch between two input clock signals which may be of different frequency and phase.
Still another object of the present invention is to provide such an improved apparatus which prevents the shrinking of the output clock period or clock width during switchover.
Yet another object of the present invention is to provide such an improved apparatus while utilizing a small number of components.


REFERENCES:
patent: 5572718 (1996-11-01), Scriber et al.
patent: 5638083 (1997-06-01), Margeson
patent: 5790609 (1998-08-01), Swoboda
patent: 5903746 (1999-05-01), Swoboda et al.
patent: 6094727 (2000-07-01), Manning

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