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Squence control circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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SRAM row redundancy

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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SRAM that can be clocked on either clock phase

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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SRAM-compatible memory for correcting invalid output data...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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SSD test systems and methods

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Stability test for silicon on insulator SRAM memory cells...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Stack trace generated code compared with database to find...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Staged startup after failover or reboot

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Staggered writing for data storage systems

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Standardized format for reporting error events occurring...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Standby processor with improved data retention

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Standby redundancy system

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent

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Standby SBC backplane

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Standby SBC backplate

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Star-I: scalable tester architecture with I-cached SIMD technolo

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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STAR-I: scalable tester architecture with I-cached SIMD technolo

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Start/stop circuit for performance counter

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Start/stop circuit for performance counter

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Starting control method, duplex platform system, and...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Starting control method, duplex platform system, and...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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