Synthesis-friendly FPGA architecture with variable length and va
System and apparatus of reconfigurable transceiver design...
System and method for a high speed, bi-directional, zero...
System and method for a switched data bus termination
System and method for adjusting a voltage
System and method for asynchronous dual bus conversion using dou
System and method for balancing capacitively coupled signal...
System and method for balancing capacitively coupled signal...
System and method for converting between CML signal logic...
System and method for creating replacements for obsolete...
System and method for device sequencing using discrete PLC...
System and method for dynamic impedance matching
System and method for dynamic modification of integrated...
System and method for dynamically executing a function in a...
System and method for dynamically executing a function in a...
System and method for dynamically reconfiguring a programmable g
System and method for effectively implementing an active...
System and method for generating a trigger signal
System and method for glitch detection in a secure...
System and method for glitch detection in a secure...