Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2008-05-13
2008-05-13
Le, Don P. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S038000, C326S046000, C326S008000
Reexamination Certificate
active
07372304
ABSTRACT:
An apparatus includes a plurality of macrocells formed from logic capable of performing one or more functions. The apparatus also includes a clock tree capable of receiving a clock signal and providing at least one copy of the clock signal to each macrocell. The clock tree includes a local branch within each macrocell, where each local branch is capable of providing at least one copy of the clock signal. In addition, the apparatus includes at least one glitch detection circuit capable of detecting a glitch in one or more copies of the clock signal provided by the local branches in the macrocells.
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European Search Report issued on Oct. 4, 2007 in European Patent Application No. 06 25 5109.
Fruhauf Serge F.
Pomet Alain C.
Jorgenson Lisa K.
Le Don P.
Munck William A.
STMicroelectronics Inc.
STMicroelectronics S.A.
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