System and method for dynamically executing a function in a...

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

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C326S047000

Reexamination Certificate

active

07417453

ABSTRACT:
A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

REFERENCES:
patent: 5744980 (1998-04-01), McGowan et al.
patent: 7054967 (2006-05-01), Plants
patent: 7111110 (2006-09-01), Pedersen
Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial; Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, Yury Markovskiy, Andre DeHon, John Wawrzynek; Aug. 25, 2000/ Version 1.0; pp. 1-31.
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs; Douglas Chang and Malgorzata Marek-Sadowska; IEEE Transactions on Computers, vol. 48, No. 6, Jun. 1999; pp. 565-578.
Scheduling Designs into a Time-Multiplexed FPGA; Steve Trimberger; Association for Computing Machine; ACM/ Sigda International Symposium on Field Programmable Gate Arrays. FPGA '98; vol. 6th Conference; Feb. 22, 1998; pp. 153-160.
Managing Pipeline-Reconfigurable FPGAs; Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, and Donald E. Thomas; ACM Sigda International Symposium on Field Programmable Gate Arrays; FPGA '98; vol. 6th Conf.; Feb. 22, 1998; pp. 55-64.

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