System and method for generating a trigger signal

Electronic digital logic circuitry – Multifunctional or programmable – Sequential or with flip-flop

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C711S100000, C712S232000

Reexamination Certificate

active

07348799

ABSTRACT:
One disclosed embodiment may comprise an application specific integrated circuit (ASIC). The ASIC includes memory that stores condition data defining conditions for enabling transitions among a plurality of states and next state data defining a next state associated with each of the respective conditions. A state machine circuit employs the condition data and the next state data to transition from a current state of the state machine circuit to a next state as a function of applying at least one condition relative to input data. The at least one condition is defined by condition data that is associated with the current state. The state machine circuit associates next state data with the at least one condition based on the current state of the state machine circuit. A control circuit provides a trigger signal in response to the current state of the state machine circuit transitioning to at least one predefined state of the plurality of states.

REFERENCES:
patent: 4791356 (1988-12-01), Warren et al.
patent: 5650734 (1997-07-01), Chu et al.
patent: 5778251 (1998-07-01), Kuroiwa et al.
patent: 5825199 (1998-10-01), Shelton et al.
patent: 5828872 (1998-10-01), Watkins
patent: 5850512 (1998-12-01), Song
patent: 5880671 (1999-03-01), Ranson et al.
patent: 5881224 (1999-03-01), Ranson et al.
patent: 5949251 (1999-09-01), Chambers
patent: 5956476 (1999-09-01), Ranson et al.
patent: 5956477 (1999-09-01), Ranson et al.
patent: 6003107 (1999-12-01), Ranson et al.
patent: 6009539 (1999-12-01), Ranson
patent: 6041371 (2000-03-01), Provence
patent: 6377912 (2002-04-01), Sample et al.
patent: 6389558 (2002-05-01), Herrmann et al.
patent: 6397354 (2002-05-01), Ertekin
patent: 6625783 (2003-09-01), Yamanaka
patent: 6732311 (2004-05-01), Fischer et al.
patent: 6754852 (2004-06-01), Swoboda
patent: 6873183 (2005-03-01), Kaviani et al.
patent: 6917220 (2005-07-01), Saito
patent: 7061272 (2006-06-01), Wilkes et al.
patent: 7159083 (2007-01-01), Samuel et al.
patent: 7228472 (2007-06-01), Johnson et al.
patent: 2003/0126508 (2003-07-01), Litt
patent: 2004/0124903 (2004-07-01), Chaudhari
patent: 2004/0193962 (2004-09-01), Johnson et al.
patent: 2004/0193976 (2004-09-01), Slaight et al.
patent: 2005/0140390 (2005-06-01), Wilkes et al.
Agilent Technologies, “Triggering a Logic Analyzer on Complex Computer Buses”, The International Engineering Consortium, (date unknown), pp. 1-17, http://www.iec.org.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

System and method for generating a trigger signal does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for generating a trigger signal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for generating a trigger signal will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3975675

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.