Use of dangling partial lines for interfacing in a PLD
Use of dangling partial lines for interfacing in a PLD
Use of dual hysteresis modes in determining a loss of signal...
Use of molecular electrostatic potential to process...
User configurable on-chip memory system
User programmable product term width expander
User-accessible freeze-logic for dynamic power reduction and...
User-accessible freeze-logic for dynamic power reduction and...
User-configurable logic circuits comprising antifuses and multip
Users registers in a reconfigurable IC
Using a single buffer for multiple I/O standards
Using a timing strobe for synchronization and validation in...
Using cascode transistors having low threshold voltages
Using observability logic for real-time debugging of ASICs
Using programmable latch to implement logic
Utilization of unused IO block for core logic functions