Using cascode transistors having low threshold voltages

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor

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326 98, 326 93, H03K 19096

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active

058217789

ABSTRACT:
In a preferred logic circuit embodiment (164), there is a signal path and a high threshold voltage transistor (46b) having a first threshold voltage and coupled to the signal path. The logic circuit further includes a precharge node (36) coupled to the signal path. The precharge node is to be precharged to a precharge voltage (V.sub.DD) during a precharge phase and operable to be discharged during an evaluate phase. The logic circuit also includes a conditional series discharge path (166) connected to the precharge node and operable to couple the precharge node to a voltage (ground) different than the precharge voltage. The conditional series discharge path includes two low threshold voltage transistors (168 and 170), each having a threshold voltage lower in magnitude than the first threshold voltage. Moreover, each low threshold voltage transistor receives a voltage connected to its gate where that voltage is disabling during the precharge phase.

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