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Digitally controlled output buffer to incrementally match line i

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Patent

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Digitally controlled pulse width adjusting circuit

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Pulse shaping
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Disturbance immune output buffer with switch and hold stages

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Patent

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Driver circuit

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
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Driver circuit

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
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Driver circuit with low power termination mode

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
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Driver circuit with self-adjusting impedance matching

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Patent

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Driver circuits

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization
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Driver for interfacing integrated circuits to transmission lines

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Patent

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Driver having inductance-controlled current slew rate

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Patent

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Driver impedance control apparatus and system

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
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Driver impedance control apparatus and system

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
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Driver impedance control mechanism

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
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Driving circuit of an output buffer stage having a high...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
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Driving circuit with load calibration and the method thereof

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
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Dual termination serial data bus with pull-up current source

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
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Dual-sided undershoot-isolating bus switch

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization
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Dynamic CMOS circuits with noise immunity

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Input noise margin enhancement
Patent

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Dynamic impedance compensation circuit and method

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
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Dynamic impedance compensation circuit and method

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
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