Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2001-06-28
2003-05-13
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S031000, C326S032000, C326S087000
Reexamination Certificate
active
06563337
ABSTRACT:
1. Field
This invention relates to circuitry for compensation of both pull-up and pull-down drivers using a single external precision resistive element and reduced interface pin count.
2. General Background
For many years, impedance controlled drivers have been implemented on circuit boards. Especially for high-speed, input/output (I/O) product design, it is important that the impedance is generally fixed over variations in process, voltage and temperature. By maintaining a generally fixed impedance, a controlled driver can maintain good signal quality between devices on the circuit board and can maintain appropriate Direct Current (DC) voltage levels and alternating current (AC) timings margins.
Commonly depending on p-channel metal-on-semiconductor (PMOS) devices, pull-up characteristics for impedance controlled drivers are independently compensated from pull-down characteristics of impedance controlled drivers, which commonly depend on n-channel metal-on-semiconductor (NMOS) devices. In many cases, for example, mechanisms are employed on a circuit board where a pull-up driver is compensated against a precision resistor terminated to ground (GND) and a corresponding pull-down driver is compensated against the pull-up driver.
One disadvantage associated with this conventional impedance control mechanism is that it is quite inaccurate because the first driver gets compensated against a precision resistor while the second driver is compensated against a non-precision resistor. Granularity of the impedance controlled driver, on-die voltage supply variations or on-die transistor channel length and width variations can erroneously set the impedance of the second driver to an inaccurate value. Of course, this inaccuracy may be avoided if the interface uses two pins and two external precision resistors for compensating the pull-up and pull-down drivers separately. However, an extra interface pin would be necessary, and thus, adversely affects interface pin minimization.
REFERENCES:
patent: 5134311 (1992-07-01), Biber et al.
patent: 5838177 (1998-11-01), Keeth
patent: 6300806 (2001-10-01), Theus et al.
patent: 6380758 (2002-04-01), Hsu et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Tokar Michael
Tran Anh Q.
LandOfFree
Driver impedance control mechanism does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Driver impedance control mechanism, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Driver impedance control mechanism will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3003839