Digitally controlled output buffer to incrementally match line i

Details Digitally controlled output buffer to incrementally match line i Digitally controlled output buffer to incrementally match line i

1995-04-03

1997-04-15

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

326 32, 326 86, 326 87, 327170, H03K 190948, H03K 190185

Patent

active

056213352

ABSTRACT:
An output buffer with a slew rate that is load independent is comprised of an output buffer (14) that is connected to an output terminal (12). The output buffer (14) is controlled such that it can drive a load (18) with different drive levels by changing the transconductance internal thereto. The transition on the input to the buffer (14) is passed through an intrinsic delay block (34) and variable delay block (40) to provide a delay signal on a node (42). A first phase detector latch (50) with a first threshold voltage compares this transition with the transition on the output terminal (12). A second phase detector latch (60) with a second threshold voltage, also compares this delayed transition with that on the output terminal (12). If both of the latches (50) and (60) indicate that the delayed transition occurred after the transition on the output terminal (12), a control signal on a line (78) is changed by incrementing a counter (74). This will increase the drive to a load (18). If the transition on the output terminal (12) occurs after the delayed transition, then the counter (74) increments the count value in the opposite direction, increasing the drive to the load (18) to increase the speed of the output driver (14).

REFERENCES:
patent: 4815113 (1989-03-01), Ludwig et al.
patent: 5134311 (1992-07-01), Biber et al.
patent: 5194765 (1993-03-01), Dunlop et al.
patent: 5220208 (1993-06-01), Schenck
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5422608 (1995-06-01), Levesque

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