Dynamic CMOS circuits with noise immunity

Details Dynamic CMOS circuits with noise immunity Dynamic CMOS circuits with noise immunity

1995-10-24

1997-07-22

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Input noise margin enhancement

326113, H03K 19003

Patent

active

056507330

ABSTRACT:
Dynamic CMOS circuits are provided with improved noise immunity. These circuits comprise first and second stacked NFET devices connected respectively between ground and a first node. An input node is coupled to the first NFET device closest to ground and a clock node coupled to the second NFET device closest to the first node. A PFET device is connected between the input node and a node formed by the stacked NFET devices. The first NFET device and the PFET device form an inverter for receiving an input signal, the switch point of the inverter being adjustable by adjusting the PFET/NFET ratio of the inverter, thereby increasing the noise immunity of the circuit.

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