Disturbance immune output buffer with switch and hold stages

Details Disturbance immune output buffer with switch and hold stages Disturbance immune output buffer with switch and hold stages

1992-03-11

1996-02-20

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 83, H03K 190185

Patent

active

054932327

ABSTRACT:
A disturbance immune output buffer is disclosed. The output buffer includes a switch stage and a hold stage. The switch stage utilizes a pull-up transistor coupled to a switch power node and a pull-down transistor coupled to a switch ground node to drive a weak signal from internal circuitry to a corresponding strong signal on an output node. The pull-up transistor and pull-down transistor are then shut off. The hold stage utilizes a pull-up transistor coupled to a hold power node and a pull-down transistor coupled to a hold ground node to maintain the signal on the output node. As a result, a constant output signal is generated which is not effected by disturbances such as transients and noise associated with ground bounce. In addition, since the switch stage transistors are shut off, any ground bounce produced during state transitions of coupled output buffers will not effect sensitive circuit elements.

REFERENCES:
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patent: 4504747 (1985-03-01), Smith et al.
patent: 4656370 (1987-04-01), Kanuma
patent: 4731553 (1988-03-01), Van Lehn et al.
patent: 4928023 (1990-05-01), Marshall
patent: 5296757 (1994-03-01), Koizumi
patent: 5319260 (1994-06-01), Wanlass
patent: 5332932 (1994-07-01), Runaldue

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