Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2007-06-05
2007-06-05
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S034000, C326S087000
Reexamination Certificate
active
10982485
ABSTRACT:
An impedance compensation circuit generates per-group pull-up impedance information and per-group pull-down impedance information to calibrate a plurality of input/output pads and dynamically updates impedance information on a per channel basis. A group refers to a group of I/O pads having similar output drive strengths in a channel. A channel refers to all I/O pads, which collectively provide a bus interface to an external device. For example, all the I/O pads interfacing with a memory module may be grouped into a channel, and address I/O pads in a channel may be arranged into a “group.” Memory I/O pads may be grouped together into a channel since memory interface pads have input/output characteristics that may be different from those of other types of I/O pads in the chip. According to one embodiment, per-group programmable offset information provides calibration information that may be different for each group in each channel.
REFERENCES:
patent: 6400546 (2002-06-01), Drapkin et al.
patent: 6445316 (2002-09-01), Hsu et al.
patent: 6541996 (2003-04-01), Rosefield et al.
patent: 2004/0044808 (2004-03-01), Salmon et al.
Ahmad Sagheer
Chen Lin
Chow Shu-Shia
Huynh Sam
Macri Joe
ATI Technologies Inc.
Tran Anh Q.
Vedder Price Kaufman & Kammholz P.C.
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