Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1999-12-21
2003-04-01
Tokar, Michael (Department: 2876)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C326S027000, C326S026000, C327S108000, C327S389000, C327S391000
Reexamination Certificate
active
06541996
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to impedance matching networks and more particularly to programmable on-chip impedance matching networks.
Background Of The Invention Input/output buffers are used in many integrated circuit applications. Conventional I/O buffers include, for example, push/pull buffer configurations that include, for example, an output driver pull up circuit and an output driver pull down circuit. I/O buffers are often connected to external or off chip pads on printed circuit boards or other integrated circuits. The I/O buffers are connected to other circuits through transmission lines, such as printed circuit boards traces or any other suitable transmission line. As is known in the art, transmission line signal distortions can result from impedance mismatches between the output buffer circuitry, and the transmission line impedance. These signal distortions can vary due to fabrication process variations, temperature variations, and other variations. Accordingly, I/O buffers have been designed to match the output impedance of the buffer with the transmission line impedance. Without proper impedance matching, overshooting, undershooting, and signal distortion can occur, particularly at high speeds.
Conventional solutions typically incorporate the use of off-chip components to implement matching termination networks. However, these can take up large amounts of board space. Other on-chip solutions require the use of separate test I/O pads for determining suitable impedance matching. For example, one external test pad is typically used to determine the suitable pull up circuit impedance whereas a separate additional test pad is used to determine suitable impedance matching for the pull down circuit of the output buffer. In addition, separate external impedance calibration resistors are used for each I/O buffer section. The use of additional test pads and additional external resistors can impact board density, reliability and cost.
Once solution, for example, as disclosed in an article entitled “Design of CMOS HSTL I/O Pads”, August 1998, by Gerald L. Esch, Jr., et al., describes an on-chip impedance matching network that provides a type of controlled impedance I/O pad by controlling a serially connected resistive element separate from the output dirvers. For example, an array of programmable resistors in the form of parallel coupled transistors, are controlled by on-chip calibration circuitry to program an on-chip impedance array by turning on and off various combinations of NFET transistors, using an up down counter. An external calibration resistor is connected to an internal chip pad. A differential amplifier is used to compare the internal pad voltage to a reference voltage. A difference between input voltages of the differential amplifier is perceived as a resistance mismatch between the external calibration resistor and the resistance of the transmission line. The differential amplifier's output is programmed as an up down counter to increment or decrement an output. The calibration is typically continuous. The article also discloses using a separate programmable resistor array for each of a pull down section and a pull up section of an output buffer. However, this can unnecessarily increase the complexity and cost of the impedance matching circuit.
In addition, solutions that employ a plurality of external calibration resistors typically duplicate the output buffer structure as the impedance compensation structure. Where two test pads and two external calibration resistors are used, the pull up circuit, such as a P channel based pull up circuit, and an N channel output buffer pull down circuit, are typically independently tested and matched during normal operation of the chip. However, using dual calibration resistors can generate unnecessary internal noise. Known programmable impedance matching circuits effectively duplicate the structure of an actual I/O buffer and the actual I/O buffer includes corresponding programmable resistor arrays that are then programmed to be identical to the impedance level determined through the I/O buffer impedance matching circuit. Typically, such I/O buffer impedance compensation circuits use, for example, an external pull up calibration resistor that has a value believed equal to be the line impedance to determine an appropriate impedance setting for the I/O pull down circuit. Similarly, an external pull down calibration resistor is coupled to ground, and is used to determine a suitable impedance level for the pull up circuit.
Accordingly, there exists a need for an impedance compensation method and circuit for an input/output buffer having an output driver pull up circuit and an output driver pull down circuit.
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Balatsos Aris
Caruk Gordon F.
Drapkin Oleg
Rosefield Peter L.
Sahdra Kuldip
ATI International SRL
Tan Vibol
Tokar Michael
Vedder, Price, Kaufman and Kammolz
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