Dual-sided undershoot-isolating bus switch

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization

Reexamination Certificate

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Details

C326S086000, C326S081000, C327S437000, C327S427000, C327S391000

Reexamination Certificate

active

06320408

ABSTRACT:

BACKGROUND OF INVENTION
This invention relates to semiconductor bus switches, and more particularly to bi-directional undershoot protection for a MOS bus switch.
Bus switches are often used in networking applications. Bus switches using metal-oxide-semiconductor (MOS) technology have low on resistance, reducing delay through the switch. The source and drain nodes of a bus-switch transistor connect to the busses while the gate is controlled by a bus-connecting enable signal. See for example Parallel Micro-Relay Bus Switch for Computer Network Communication with Reduced Crosstalk and Low On-Resistance using Charge Pumps, U.S. Pat. No. 5,808,502, and Bus Switch Having Both P- and N-Channel Transistors for Constant Impedance Using Isolation Circuit for Live-Insertion when Powered Down U.S. Pat. No. 6,034,553.
More complex networks are emerging. For example, the bus switch may connect two processor buses. Each processor bus can operate independently of the other. Hot-plugging or hot-swapping of card with the processor bus can also occur. When the bus switch is in the isolation mode, full isolation must occur, regardless of which bus is active.
FIG. 1
shows a typical application of a bus switch. First local bus signals
18
(bus A) is connected to CPU_A
10
, memory_A
14
, and Application-Specific Integrated Circuit (ASIC_A)
12
. Second local bus signals
19
(bus B) is a second local bus that has CPU_B
11
, memory_B
15
, and Application-Specific Integrated Circuit (ASIC_B)
13
. Second local bus signals
19
is a hot-plugable bus. Switch network
16
connects address, data, and control lines from bus signals
18
to bus signals
19
using MOS transistors. One transistor is used for each bus signal.
When a device is plugged into bus signals
19
, it may be desired to isolate bus signals
19
from local bus signals
18
. Noise caused by the plugging operation can then be isolated to bus signals
19
, allowing local bus signals
18
to operate unhindered. Switch network
16
can isolate bus signals
19
from local bus signals
18
by applying a low voltage to n-channel transistors in switch network
16
. When switch network
16
isolates, Bus_A can operate independently of Bus_B.
Either Bus_A or Bus_B may be hot-plugged into the other bus. This allows for repair of systems without any downtime. Isolation by switch network
16
must therefore be fully bi-directional since it is not known which bus will be replaced until a failure occurs.
Undershoot Problem
When an n-channel transistor is used as the bus switch, the bus switch is disabled by driving a ground voltage to the gate of the n-channel bus-switch transistor. The output bus signal should be isolated from voltage changes at the input bus signal. The quality of the signal waveforms on local bus signal
18
is not always well controlled. Sometime large voltage spikes below ground (undershoots) occur, especially on the high-to-low transitions from high-current drivers on local bus signal
18
. The same could occur on bus signals
19
.
When the bus-switch input from bus signal
18
goes below ground, a positive gate-to-source voltage develops on bus-switch transistor since its gate is at ground. A conducting channel forms below the gate. When the undershoot is greater than a volt, this gate-to-source voltage exceeds the n-channel threshold voltage, turning on the n-channel bus switch transistor. Some current is conducted through the channel of the bus-switch transistor even though its gate may be kept at ground. The result is that the voltage is disturbed on the drain of the bus-switch transistor, and the output to bus signals
19
.
When the source of the n-channel bus-switch transistor goes negative during the undershoot, the base-emitter junction of the parasitic lateral NPN transistor is forward biased, coupling more current to the output through the p-type substrate.
The result of the undershoot is that the output connects to the input for a short period of time, the duration of the undershoot. The voltage on the drain of the bus-switch transistor can quickly fall from the power supply (Vcc) to ground and even below ground should the undershoot last for more than a few nanoseconds. The undershoots on the input bus coupled to the output, producing severe voltage disturbances on the isolated bus.
The inventor has solved an undershoot-isolation problem in earlier patents, such as U.S. Pat. No. 6,052,019 for Undershcot-lsolating MOS Bus Switch. However, this patent shows a circuit that is effective when the undershoot always occurs on only one side of the bus switch. Another improved circuit using a pulse generator was shown by the inventor in “Bi-Directional Undershoot-Isolating Bus Switch with Directional Control”, U.S. Ser. No. 09/607,460, filed Jun. 29, 2000. While useful, a fully bi-directional undershoot-isolating bus switch without the pulse generator is desired.


REFERENCES:
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patent: 4945267 (1990-07-01), Galbraith
patent: 5442304 (1995-08-01), Wong et al.
patent: 5444397 (1995-08-01), Wong et al.
patent: 5502329 (1996-03-01), Pezzani
patent: 5751168 (1998-05-01), Speed, III et al.
patent: 5808502 (1998-09-01), Hui et al.
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patent: 6034553 (2000-03-01), Kwong
patent: 6052019 (2000-04-01), Kwong
patent: 6069493 (2000-05-01), Pigott et al.
patent: 6100719 (2000-08-01), Graves et al.
patent: 6236259 (2001-05-01), Goodell et al.

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