Scalable serializer-deserializer architecture and...

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

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C326S037000, C326S041000, C326S047000, C326S101000

Reexamination Certificate

active

07098685

ABSTRACT:
Systems and methods are disclosed to provide programmable input/output functionality for a programmable logic device. For example, in accordance with one embodiment of the present invention, a programmable interface selectively employs a scalable serializer-deserializer and clock and data recovery circuit. The programmable interface further includes programmable input/output buffers and embedded memory to allow the programmable logic device to support a wide range of input/output interface standards.

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patent: WO 01/69837 (2001-03-01), None
“Converting Wide, Parallel Data Buses to High Speed Serial Links,” by Jason Konstas, International IC '99, Conference Proceedings, pp. 19-30, no month.
U.S. Appl. No. 10/023,226 to Am P. Agrawal et al., filed Dec. 14, 2001, with Preliminary Amendment.

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