Scalable device architecture for high-speed interfaces

Details Scalable device architecture for high-speed interfaces Scalable device architecture for high-speed interfaces

2005-06-07

2005-06-07

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Significant integrated structure, layout, or layout...

C326S041000, C326S038000

Reexamination Certificate

active

06903575

ABSTRACT:
An architecture is disclosed to provide high-speed input/output interface capabilities for programmable devices. One or more configurable input/output circuits are situated between the input/output drivers and the programmable core circuitry of the programmable device. The input/output circuits are optimized for the high-speed requirements of the input/output interface standards, with each input/output circuit configurable to support numerous, different input/output interface standards. The programmable core circuitry may be utilized to support the lower-speed requirements of the input/output interface standards.

REFERENCES:
patent: 6426649 (2002-07-01), Fu et al.
patent: 6483343 (2002-11-01), Faith et al.
patent: 6608500 (2003-08-01), Lacey et al.
patent: 6674303 (2004-01-01), Morse et al.
U.S. Appl. No. 10/425,862, filed Apr. 28, 2003, entitled “Programmable And Fixed Logic Circuitry For High-Speed Interfaces”.

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