Scalable shared network memory switch for an FPGA

Details Scalable shared network memory switch for an FPGA Scalable shared network memory switch for an FPGA

2005-10-25

2008-10-21

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C326S040000

Reexamination Certificate

active

07439763

ABSTRACT:
A shared memory switch is provided for storing and retrieving data from BlockRAM (BRAM) memory of a PLD. A set of class queues maintain a group of pointers that show the location of the incoming “cells” or “packets” stored in the memory in the switch based on the time of storage in the BRAM. A non-blocking memory architecture is implemented that allows for a scalable N×N memory structure to be created (N=number of input and output ports). A write controller stripes the data across this N×N memory to prevent data collisions on read in or read out of data. The data is scheduled for read out of this N×N shared memory buffer based on priorities or classes in the class queues, with priorities being set by a user, and then data is read out from the BRAM.

REFERENCES:
patent: 5166927 (1992-11-01), Iida et al.
patent: 5469003 (1995-11-01), Kean
patent: 5606562 (1997-02-01), Landguth
patent: 5610914 (1997-03-01), Yamada
patent: 5841771 (1998-11-01), Irwin et al.
patent: 5953336 (1999-09-01), Moore et al.
patent: 6160813 (2000-12-01), Banks et al.
patent: 6480911 (2002-11-01), Lu
patent: 6546017 (2003-04-01), Khaunte
Nikologiannis, A.; Katevenis, M., “Effcient per-flow queuering in DRAM at OC-192 line rate using out-of-order execution techniques”; Communications, 2001. ICC 2001. IEEE International Conference on vol. 7, Jun. 11-14, 2001 pp. 2048-2052 vol. 7 Digital Object Identifier 10. 1109/ICC.2001.937019.
Sundar Iyer, Amr Awadallah, Nick McKeown, “Analysis of a packet switch with memories running slower than the line-rate,” Stanford university computer system laboratory, May 2000., 1-47 pgs.
Amit Prakash, Sadia Sharif, Adnan Aziz, “An O(log2N) parallel algorithm for out put queuing,” University of Texas at Austin, 2002, 0-7803-7476-Feb. 02, 2002 IEEE, 7 pgs.
Biplab Sikdar et al., “An Integrated Model For the Latency and Steady-State Throughtout of TCP Connections”, Dept. of Electrical Computer Science Engineering, Rensselaer Polytechnic Institute, Performance Evaluation, vol. 46, no. 2-3 pgs. 139-154, Oct. 2001. (ABSTRACT).
Mutlu Arpaci, John Copeland, “Buffer Management for Shared Memory ATM Switches”, IEEE Communication Surveys, http://www.comsoc.org/pubs/surveys, First Quarter 2000, 1-10 pgs.
Andreas Frey, Yoshita Takahashi, “A note on an M/G1/1/N queue with vacation time and exhaustive serivce discipline,” Ntt Multimedia Network Laboratories.
Manjunath, D.; Sikdar, B.; “Variabel Length Packet Switches: Delay Analysis of Crossbar Switches under Poisson and Self Similar Traffic”, INFOCOM 2000. 19th Annual Joint Conference of the IEEE Computer and Communications Societies. Proceedings. IEEE vol. 2, Mar. 26-30, 2000 pp. 1055-1064 vol. 2 Digital Object Identifier 10.1109/INFCOM.2000.832281.
11/259,394, filed Oct. 25, 2005, Kavipurapu G. N. et al., entitled “Time Based Data Storage for shared Network Memory Switch”, 23 pgs., XILINX, Inc. 2100 Logic Drive, San Jose California, 95124.
11/258,683, filed Oct. 25, 2005, Kavipurapu G. N. et al., entitled “Striping of Data into Memory of a Network Data Switch to Prevent Read and Write Collisions”, 24 pgs., XILINX, Inc. 2100 Logic Drive, San Jose California, 95124.
11/258,682, filed Oct. 25, 2005, Kavipurapu G. N. et al., entitled “Class Queue for Network Data Switch to Identify Data Memory Locations by Arrival Time”, 23 pgs., XILINX, Inc. 2100 Logic Drive, San Jose California, 95124.
Massiglia, Paul, The RAID Book, RAID Advisory Board, 6th Edition, Chapter 4: Disk Striping and Mirroring, Feb., 1997, pp. 84-85.

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