Scaleable padframe interface circuit for FPGA yielding improved

Details Scaleable padframe interface circuit for FPGA yielding improved Scaleable padframe interface circuit for FPGA yielding improved

1997-11-25

2000-10-10

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 41, 326 38, H03K 19173, H03K 19177

Patent

active

061305502

ABSTRACT:
An interface circuit for use in the layout of padframe interface circuits for field programmable gate arrays having a plurality of I/O cells each of which may be programmed as an input or an output (or both) and a programmable connection matrix which provide programmable pathways between the data output signals generated by the core array of logic blocks and I/O cells programmed as outputs and provide programmable pathways between I/O cells programmed as inputs and data input conductors going into the core array. The interface circuits are all substantially identical in structure, and each includes a sufficient number of power and ground connections to supply adequate current to the number of I/O cells the interface has. Each interface circuit also includes at least one and preferably two open spaces into which conductive paths may be laid out to carry power to the core array or carry dedicated signals to circuits other than the core which also reside on the integrated circuit. Because of the substantially identical structure of each interface and the preservation of ratios between I/O cells, power and ground connections and open slots, larger or smaller core arrays may be accommodated by cutting and pasting additional interface circuits into the layout thereby substantially decreasing design, placement and layout time and time to market for introduction of new FPGAs in a family with larger core arrays. The regular repeatable structure of RIU's simplifies software development for products within the family and as such contributes to faster "time to market".

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