Sample and load scheme for observability of internal nodes in a

Details Sample and load scheme for observability of internal nodes in a Sample and load scheme for observability of internal nodes in a

1996-03-11

1998-06-09

Santamauro, Jon

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 16, 326 39, 371 222, H03K 19177, G01R 313177

Patent

active

057640793

ABSTRACT:
A programmable logic device (PLD) that provides the capability to observe and control the logic state of buried internal nodes is disclosed. The PLD provides shadow storage units for internal nodes such as logic element registers, memory cells, and I/O registers. A sample/load data path includes bidirectional data buses and shift register that facilitate the sampling of internal nodes for observing their logic states, and loading of internal nodes for controlling their logic states.

REFERENCES:
patent: 4864579 (1989-09-01), Kishida et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5497475 (1996-03-01), Alapat
patent: 5581198 (1996-12-01), Trimberger

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