Bus operation circuit using CMOS ratio logic circuits

Details Bus operation circuit using CMOS ratio logic circuits Bus operation circuit using CMOS ratio logic circuits

1997-02-21

1998-05-26

Shah, Alpesh M.

Electronic digital logic circuitry

Multifunctional or programmable

Array

395308, 326 86, G06F 1300

Patent

active

057581797

ABSTRACT:
A match bus operation circuit is disclosed for detecting load/store conflicts created by out-of-order instruction execution in a superscalar microprocessor having first and second busses. A ratio logic compare circuit generates a match bus indicating a match or conflict between the first and second busses. A ratio logic priority circuit is coupled to the ratio logic compare circuit for receiving the match bus and generating a priority bus indicating a first match of the match bus. A ratio logic mask circuit is also coupled to the ratio logic compare circuit for receiving the match bus and generating a mask bus that flags all instructions after the first match for discarding. A ratio logic multiple hit circuit is also coupled to the ratio logic compare circuit and indicates whether more than one instruction has matched.

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