Processor configured to predecode relative control transfer...

Processor configured to select a next fetch address by partially

Processor configured to selectively cancel instructions from...

Processor configured to selectively free physical registers...

Processor containing data path units with forwarding paths...

Processor controller for accelerating instruction issuing rate

Processor core and method for managing program counter...

Processor coupled by visible register set to modular...

Processor device for out-of-order processing having...

Processor E-unit to I-unit interface instruction...

Processor employing multiple register sets to eliminate interrup

Processor executing plural instruction sets (ISA's)...

Processor executing SIMD instructions

Processor executing SIMD instructions

Processor executing unpack instruction to interleave data...

Processor execution, pipeline sharing instruction, and data...

Processor for executing an instructions stream where instruction

Processor for executing highly efficient VLIW

Processor for executing highly efficient VLIW

Processor for executing instruction codes of two different...