Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2006-10-03
2006-10-03
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
Reexamination Certificate
active
07117344
ABSTRACT:
A processor execution pipeline that includes, a stage latch circuit and a stage latch circuit provided at an input stage of a first processing stage for holding a first processing data SOURCE1and a second processing data, respectively; an operator provided at the first processing stage for executing a processing by using the first processing data SOURCE1and the second processing data; a stage latch circuit provided between the first processing stage and a second processing stage for holding an output value of the operator; an operator provided at the second processing stage for executing the processing by using a value of the stage latch circuit when an instruction has been decoded; and an instruction decoder that decodes the instruction to the operator as a through instruction to pass the value of the stage latch circuit through this operator.
REFERENCES:
patent: 5165034 (1992-11-01), Kanuma
patent: 5325495 (1994-06-01), McLellan
patent: 5333284 (1994-07-01), Nugent
patent: 5471626 (1995-11-01), Carnevale et al.
patent: 5619664 (1997-04-01), Glew
patent: 5740181 (1998-04-01), Heikes et al.
patent: 5918034 (1999-06-01), Petolino, Jr.
patent: 5928355 (1999-07-01), Petolino, Jr.
patent: 5930492 (1999-07-01), Lynch
patent: 5996065 (1999-11-01), Makineni et al.
patent: 6012139 (2000-01-01), Biswas et al.
patent: 6049860 (2000-04-01), Krygowski et al.
patent: 6460134 (2002-10-01), Blomgren et al.
patent: SH058-106636 (1983-06-01), None
patent: HEI 6-222920 (1994-08-01), None
patent: HEI 8-87411 (1996-04-01), None
InstantWeb. Free Online Computing Dictionary. © 1995. Search Term: Latch http://www.instantweb.com/foldoc/foldoc.cgi?query=latch.
Texas Instruments. “Semiconductor Service and Support: Digital Compression Glossary of Terms”. © Jun. 1994. Term: Decoder http://www.ti.com/sc/docs/glossary/94056.htm.
Japanese Office Action dated Aug. 23, 2005 for App. No. HEI11-284850 (6 pgs).
Chan Eddie
Fujitsu Limited
Li Aimee J.
Staas & Halsey , LLP
LandOfFree
Processor execution, pipeline sharing instruction, and data... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Processor execution, pipeline sharing instruction, and data..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor execution, pipeline sharing instruction, and data... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3674767